In the formation of integrated circuits, silicon technology for ultra-large scale integration (ULSI) has advanced to the point where several million devices may be included on a single semiconductor wafer die. In order to achieve such high device packing densities, multilevel interconnects are required. In general, a multilevel interconnect may be required to connect separate devices or conductors located in spatially separated planes on the wafer. It may be necessary, for instance, to connect a conductor line or buried contact on a first plane of the wafer with a second conductor line on a second plane of the wafer (either above or below). This process is often referred to as planarization of wafer topography.
In the past, during semiconductor fabrication, contact plugs have been deposited in holes or trenches in an oxide layer. These contacts formed or planarized by techniques such as chemical vapor deposition CVD. In general, contact hole planarization remains among the most difficult and critical semiconductor fabrication processes. Among the problems are high Si consumption, poor film adhesion, and loss of selectivity on dielectrics.
Planarization methods involving selective CVD tungsten as a contact plug are often utilized. These processes are difficult to stably reproduce. Additionally, with these processes, it is often difficult to achieve low contact resistance on P-type diffusion layers.
The present invention is directed to a novel method in which the contact plugs rather than being defined by holes or trenches in the oxide are defined by oxide spacers of prior conducting layers. This method overcomes many of the aforementioned prior art problems and forms conducting pillars which can be self-aligned with respect to other conductors.